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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">ICH_VTR, Interrupt Controller VGIC Type Register</h1><p>The ICH_VTR characteristics are:</p><h2>Purpose</h2>
        <p>Reports supported GIC virtualization features.</p>
      <h2>Configuration</h2><p>AArch32 System register ICH_VTR bits [31:0] are architecturally mapped to AArch64 System register <a href="AArch64-ich_vtr_el2.html">ICH_VTR_EL2[31:0]</a>.</p><p>This register is present only when EL2 is capable of using AArch32, FEAT_GICv3 is implemented and (EL2 is implemented or EL3 is implemented). Otherwise, direct accesses to ICH_VTR are <span class="arm-defined-word">UNDEFINED</span>.</p>
        <p>If EL2 is not implemented, all bits in this register are <span class="arm-defined-word">RES0</span> from EL3, except for nV4, which is <span class="arm-defined-word">RES1</span> from EL3.</p>
      <h2>Attributes</h2>
        <p>ICH_VTR is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="3"><a href="#fieldset_0-31_29">PRIbits</a></td><td class="lr" colspan="3"><a href="#fieldset_0-28_26">PREbits</a></td><td class="lr" colspan="3"><a href="#fieldset_0-25_23">IDbits</a></td><td class="lr" colspan="1"><a href="#fieldset_0-22_22">SEIS</a></td><td class="lr" colspan="1"><a href="#fieldset_0-21_21">A3V</a></td><td class="lr" colspan="1"><a href="#fieldset_0-20_20">nV4</a></td><td class="lr" colspan="1"><a href="#fieldset_0-19_19">TDS</a></td><td class="lr" colspan="14"><a href="#fieldset_0-18_5">RES0</a></td><td class="lr" colspan="5"><a href="#fieldset_0-4_0">ListRegs</a></td></tr></tbody></table><h4 id="fieldset_0-31_29">PRIbits, bits [31:29]</h4><div class="field"><p>Priority bits. The number of virtual priority bits implemented, minus one.</p>
<p>An implementation must implement at least 32 levels of virtual priority (5 priority bits).</p>
<p>This field is an alias of <a href="AArch32-icv_ctlr.html">ICV_CTLR</a>.PRIbits.</p></div><h4 id="fieldset_0-28_26">PREbits, bits [28:26]</h4><div class="field"><p>The number of virtual preemption bits implemented, minus one.</p>
<p>An implementation must implement at least 32 levels of virtual preemption priority (5 preemption bits).</p>
<p>The value of this field must be less than or equal to the value of ICH_VTR.PRIbits.</p></div><h4 id="fieldset_0-25_23">IDbits, bits [25:23]</h4><div class="field">
      <p>The number of virtual interrupt identifier bits supported:</p>
    <table class="valuetable"><tr><th>IDbits</th><th>Meaning</th></tr><tr><td class="bitfield">0b000</td><td>
          <p>16 bits.</p>
        </td></tr><tr><td class="bitfield">0b001</td><td>
          <p>24 bits.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>This field is an alias of <a href="AArch32-icv_ctlr.html">ICV_CTLR</a>.IDbits.</p></div><h4 id="fieldset_0-22_22">SEIS, bit [22]</h4><div class="field">
      <p>SEI Support. Indicates whether the virtual CPU interface supports generation of SEIs:</p>
    <table class="valuetable"><tr><th>SEIS</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>The virtual CPU interface logic does not support generation of SEIs.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>The virtual CPU interface logic supports generation of SEIs.</p>
        </td></tr></table>
      <p>This bit is an alias of <a href="AArch32-icv_ctlr.html">ICV_CTLR</a>.SEIS.</p>
    </div><h4 id="fieldset_0-21_21">A3V, bit [21]</h4><div class="field">
      <p>Affinity 3 Valid. Possible values are:</p>
    <table class="valuetable"><tr><th>A3V</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>The virtual CPU interface logic only supports zero values of Affinity 3 in SGI generation System registers.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>The virtual CPU interface logic supports nonzero values of Affinity 3 in SGI generation System registers.</p>
        </td></tr></table>
      <p>This bit is an alias of <a href="AArch32-icv_ctlr.html">ICV_CTLR</a>.A3V.</p>
    </div><h4 id="fieldset_0-20_20">nV4, bit [20]</h4><div class="field">
      <p>Direct injection of virtual interrupts not supported. Possible values are:</p>
    <table class="valuetable"><tr><th>nV4</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>The CPU interface logic supports direct injection of virtual interrupts.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>The CPU interface logic does not support direct injection of virtual interrupts.</p>
        </td></tr></table>
      <p>In GICv3, the only permitted value is <span class="binarynumber">0b1</span>.</p>
    </div><h4 id="fieldset_0-19_19">TDS, bit [19]</h4><div class="field">
      <p>Separate trapping of Non-secure EL1 writes to <a href="AArch32-icv_dir.html">ICV_DIR</a> supported.</p>
    <table class="valuetable"><tr><th>TDS</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Implementation does not support <a href="AArch32-ich_hcr.html">ICH_HCR</a>.TDIR.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Implementation supports <a href="AArch32-ich_hcr.html">ICH_HCR</a>.TDIR.</p>
        </td></tr></table>
      <p>FEAT_GICv3_TDIR implements the functionality added by the value <span class="binarynumber">0b1</span>.</p>
    </div><h4 id="fieldset_0-18_5">Bits [18:5]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-4_0">ListRegs, bits [4:0]</h4><div class="field">
      <p>The number of implemented List registers, minus one. For example, a value of <span class="binarynumber">0b01111</span> indicates that the maximum of 16 List registers are implemented.</p>
    </div><div class="access_mechanisms"><h2>Accessing ICH_VTR</h2><p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">MRC{&lt;c&gt;}{&lt;q&gt;} &lt;coproc&gt;, {#}&lt;opc1&gt;, &lt;Rt&gt;, &lt;CRn&gt;, &lt;CRm&gt;{, {#}&lt;opc2&gt;}</h4><table class="access_instructions"><tr><th>coproc</th><th>opc1</th><th>CRn</th><th>CRm</th><th>opc2</th></tr><tr><td>0b1111</td><td>0b100</td><td>0b1100</td><td>0b1011</td><td>0b001</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HSTR_EL2.T12 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HSTR.T12 == '1' then
        AArch32.TakeHypTrapException(0x03);
    else
        UNDEFINED;
elsif PSTATE.EL == EL2 then
    if ICC_HSRE.SRE == '0' then
        UNDEFINED;
    else
        R[t] = ICH_VTR;
elsif PSTATE.EL == EL3 then
    if ICC_MSRE.SRE == '0' then
        UNDEFINED;
    else
        R[t] = ICH_VTR;
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:05; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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